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Feng Li, Ph.D.

Feng Li, Ph.D., P.E.

Micron Endowed Chair in Microelectronics, NGeM Director, FIB/SEM Director

Office

Gauss-Johnson 217

Phone

208-885-7571

Mailing Address

Electrical and Computer Engineering
University of Idaho
875 Perimeter Drive, MS 1023
Moscow, ID 83844-1023

  • Ph.D., University of Wisconsin-Milwaukee
  • M.S., University of Texas at Arlington
  • M.S., Beijing University of Post and Telecommunications
  • B.S., Ocean University of China

  • ECE 310 Microelectronics I
  • ECE 311 Microelectronics I Lab
  • EC 330 Electromagnetic Theory
  • ECE 331 Electromagnetics Lab
  • ECE 350 Signals and Systems I
  • ECE 351 Signals and Systems I Lab
  • ECE 418/518 Introduction to Electronic Packaging
  • ECE 445 Introduction to VLSI Design
  • ECE 460 Semiconductor Devices
  • ECE 465/565 Introduction to Microelectronics Fabrication
  • ECE 480/482 Senior Design I
  • ECE 481/483 Senior Design II

  • Semiconductor device and IC design
  • Micro/nanofabrication and electronic packaging
  • ML/AI in VLSI design and manufacturing

Feng Li received his Ph.D. in electrical engineering from the University of Wisconsin-Milwaukee, WI, USA, in 2012. He was previously with Duke University, Durham, NC, USA, and the University of Texas at Arlington, TX, USA. He joined the University of Idaho, Moscow, ID, USA, as an Assistant Professor of electrical and computer engineering in 2014 and was promoted to Associate Professor in 2020. He was named the Micron Endowed Professor in Microelectronics in 2022. His research interests include 3-D IC integration and packaging, silicon and compound semiconductor devices and ICs, and micro/nanofabrication. Dr. Li is a Senior Member of IEEE.

  • F. Li and J. Shi, "Metal-to-Metal Flip-Chip Bonding for High-Temperature 3D SiC IC Integration and Packaging," 2023 IEEE Workshop on Microelectronics and Electron Devices (WMED), Boise, ID, USA, 2023, pp. 1-4, doi: 10.1109/WMED58543.2023.10097447
  • X. Chen, F. Li, and H. Hess, "Trench Gate β-Ga₂O₃ MOSFETs: A Review," Engineering Research Express, vol. 5, no. 1, pp. 1-14, March 2023. DOI: 10.1088/2631-8695/acc00c
  • F. Li, "3D Stacking of SiC Integrated Circuit Chips with Gold Wire Bonded Interconnects for Long-Duration High-Temperature Applications," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 10, pp. 1601-1608, October 2022. DOI: 10.1109/TCPMT.2022.3210477
  • F. Li and S. Raveendran, "Wirebonding Based 3-D SiC IC Stacks for High Temperature Applications," 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2022, pp. 2023-2027, doi: 10.1109/ECTC51906.2022.00319
  • N. Totorica, F. Li, “Signal and power integrity challenges for high-density system-on-package,” Semiconductor Science and Information Devices, Vol. 4, no. 2, pp. 1-9, October 2022. DOI: 10.30564/ssid.v4i2.4475.
  • M. D. Cino and F. Li, "Flip chip die-to-wafer bonding review: gaps to high volume manufacturing," Semiconductor Science and Information Devices, vol. 4, no. 1, pp. 8-13, 2022. DOI: 10.30564/ssid.v4i1.4474
  • W. Hu and F. Li, “Scaling beyond 7nm node: an overview of gate-all-around FETs,” 2021 9th International Symposium on Next Generation Electronics (ISNE), pp. 1-6, doi: 10.1109/ISNE48910.2021.9493305
  • M. Shawon, and F. Li, “A review of the building blocks of silicon photonics: from fabrication perspective,” Semiconductor Science and Information Devices, vol. 1, no. 1, pp. 29-35, October 2019.
  • F. Li, “S electrode materials,” in Inorganic Battery Materials, H. Wang and B. Fokwa, Eds. John Wiley & Sons, pp. 1-14, June 2019.
  • Q. Li, F. Li, and A. W. Owens, “Microbump processing for 3D IC integration,” 15th International Conference and Exhibition on Device Packaging, vol. 2019, No. DPC, pp. 1028-1049, January 2019.
  • M. Binggeli, and F. Li, “Scaling optical communication for on-chip interconnect,” 19th International Conference on Electronic Packaging Technology (ICEPT), pp. 1178-1183, August 2018.
  • Y. Yang and F. Li, "Recent Advances in 3D Packaging for Medical Applications," 19th International Conference on Electronic Packaging Technology (ICEPT), pp. 1193-1197, August 2018.
  • Y. S. Wase, and F. Li, “Technology review of system in package,” 15th International Conference and Exhibition on Device Packaging, vol. 2017, No. DPC, pp. 1-20, January 2017.
  • F. Li, Q. Liu, and D. P. Klemer, “Numerical simulation of high electron mobility transistors based on the spectral element method,” Applied Computational Electromagnetics Society Journal, vol. 31, no. 10, pp. 1144-1150, October 2016.
  • F. Li, Q. Liu, D. P. Klemer, “Plasmon resonance effects in GaAs/AlGaAs heterojunction devices: an analysis based on spectral element simulation,” IEEE Transactions on Electron Devices, vol. 61, no. 5, pp. 1477-1482, May 2014.

Contact Us

Buchanan Engineering Building Rm. 213

Mailing Address:

Electrical & Computer Engineering
University of Idaho
875 Perimeter Drive MS 1023
Moscow, ID 83844-1023

Phone: 208-885-6554

Fax: 208-885-7579

Email: ece-info@uidaho.edu